lpc43xx数据手册（lpc4357/lpc4350等芯片手册） -九游会网页

包括 nxp  lpc4357/lpc4350/lpc4353/lpc4337/lpc4333/lpc4330/lpc4320/lpc4310芯片手册

the lpc43xx are arm cortex-m4 based microcontrollers for embedded applications which include an arm cortex-m0 coprocessor, up to 1 mb of flash, up to 264 kb of sram, advanced configurable peripherals such as the state configurable timer (sct) and the serial general purpose i/o (sgpio) interface, two high-speed usb controllers, ethernet, lcd, an external memory controller, and multiple digital and analog peripherals.

the lpc43xx operate at cpu frequencies of up to 204 mhz.the arm cortex-m4 is a next generation 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. the arm cortex-m4 cpu incorporates a 3-stage pipeline, uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching.

the arm cortex-m4 supports single-cycle digital signal processing and simd instructions. a hardware floating-point processor is integrated in the core. the arm cortex-m0 coprocessor is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the cortex-m4 core. the cortex-m0 coprocessor, designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 mhz performance with a simple instruction set and reduced code size.

• cortex-m4 processor core

– arm cortex-m4 processor, running at frequencies of up to 204 mhz.

– arm cortex-m4 built-in memory protection unit (mpu) supporting eight regions.

– arm cortex-m4 built-in nested vectored interrupt controller (nvic).

– hardware floating-point unit.

– non-maskable interrupt (nmi) input.

– jtag and serial wire debug (swd), serial trace, eight breakpoints, and four

watch points.

– enhanced trace module (etm) and enhanced trace buffer (etb) support.

– system tick timer.

• cortex-m0 processor core

– arm cortex-m0 co-processor capable of off-loading the main arm cortex-m4

application processor.

– running at frequencies of up to 204 mhz.

– jtag, serial wire debug, and built-in nvic.

• on-chip memory (flashless parts)

– up to 264 kb sram for code and data use.

– multiple sram blocks with separate bus access. two sram blocks can be

powered down individually.

– 64 kb rom containing boot code and on-chip software drivers.

– 32 bit general-purpose one-time programmable (otp) memory.

• on-chip memory (parts with on-chip flash)

– up to 1 mb on-chip dual bank flash memory with flash accelerator.

– 16 kb on-chip eeprom data memory.

– 136 kb sram for code and data use.

– multiple sram blocks with separate bus access. two sram blocks can be

powered down individually.

– 64 kb rom containing boot code and on-chip software drivers.

– 128 bit general-purpose one-time programmable (otp) memory.

• configurable digital peripherals

– serial gpio (sgpio) interface.

– state configurable timer (sct) subsystem on ahb.

– global input multiplexer array (gima) allows to cross-connect multiple inputs and

outputs to event driven peripherals like the timers, sct, and adc0/1.

• serial interfaces

– quad spi flash interface (spifi) with 1-, 2-, or 4-bit data at rates of up to 60 mb

per second.

– 10/100t ethernet mac with rmii and mii interfaces and dma support for high

throughput at low cpu load. support for ieee 1588 time stamping and advanced

time stamping (ieee 1588-2008 v2).

– one high-speed usb 2.0 host/device/otg interface with dma support and

on-chip high-speed phy.

– one high-speed usb 2.0 host/device interface with dma support, on-chip

full-speed phy and ulpi interface to external high-speed phy.

– usb interface electrical test software included in rom usb stack.

– one 550 uart with dma support and full modem interface.

– three 550 usarts with dma and synchronous mode support and a smart card

interface conforming to iso7816 specification. one usart with irda interface.

– two c_can 2.0b controllers with one channel each.

– two ssp controllers with fifo and multi-protocol support. both ssps with dma

support.

– one spi controller.

– one fast-mode plus i2c-bus interface with monitor mode and with open-drain i/o

pins conforming to the full i2c-bus specification. supports data rates of up to

1 mbit/s.

– one standard i2c-bus interface with monitor mode and with standard i/o pins.

– two i2s interfaces, each with dma support and with one input and one output.

• digital peripherals

– external memory controller (emc) supporting external sram, rom, nor flash,

and sdram devices.

– lcd controller with dma support and a programmable display resolution of up to

1024h  768v. supports monochrome and color stn panels and tft color

panels; supports 1/2/4/8 bpp color look-up table (clut) and 16/24-bit direct pixel

mapping.

– secure digital input output (sd/mmc) card interface.

– eight-channel general-purpose dma (gpdma) controller can access all

memories on the ahb and all dma-capable ahb slaves.

– up to 164 general-purpose input/output (gpio) pins with configurable

pull-up/pull-down resistors.

– gpio registers are located on the ahb for fast access. gpio ports have dma

support.

– up to eight gpio pins can be selected from all gpio pins as edge and level

sensitive interrupt sources.

– two gpio group interrupt modules enable an interrupt based on a programmable

pattern of input states of a group of gpio pins.

– four general-purpose timer/counters with capture and match capabilities.

– one motor control pulse width modulator (pwm) for three-phase motor control.

– one quadrature encoder interface (qei).

– repetitive interrupt timer (ri timer).

– windowed watchdog timer (wwdt).

– ultra-low power real-time clock (rtc) on separate power domain with 256 bytes

of battery powered backup registers.

– (parts with on-chip flash only): event recorder with three inputs to record event

identification and event time; can be battery powered.

– alarm timer; can be battery powered.

• analog peripherals

– one 10-bit dac with dma support and a data conversion rate of 400 ksamples/s.

– two 10-bit adcs with dma support and a data conversion rate of 400 ksamples/s.

up to eight input channels per adc.

• security (lpc43sxx only)

– aes decryption programmable through an on-chip api.

– two 128-bit secure otp memories for aes key storage and customer use.

– random number generator (rng) accessible through aes api.

– unique id for each device.

• clock generation unit

– crystal oscillator with an operating range of 1 mhz to 25 mhz.

– 12 mhz internal rc (irc) oscillator trimmed to 1 % accuracy over temperature

and voltage.

– ultra-low power real-time clock (rtc) crystal oscillator.

– three plls allow cpu operation up to the maximum cpu rate without the need for

a high-frequency crystal. the second pll is dedicated to the high-speed usb, the

third pll can be used as audio pll.

– clock output.

• power

– single 3.3 v (2.2 v to 3.6 v) power supply with on-chip dc-to-dc converter for the

core supply and the rtc power domain.

– rtc power domain can be powered separately by a 3 v battery supply.

– four reduced power modes: sleep, deep-sleep, power-down, and deep

power-down.

– processor wake-up from sleep mode via wake-up interrupts from various

peripherals.

– wake-up from deep-sleep, power-down, and deep power-down modes via

external interrupts and interrupts generated by battery powered blocks in the rtc

power domain.

– brownout detect with four separate thresholds for interrupt and forced reset.

– power-on reset (por).

– available as lbga256, tfbga180, and tfbga100 packages and as lqfp208

and lqfp144 packages.