h5ps1g63jfr ddr2 sdram内存芯片用户手册 -九游会网页

h5ps1g63jfr ddr2 sdram内存芯片用户手册

使用该芯片的有：

myd-sam9g15 工控板/开发板/核心板

myd-sam9g25 工控板/开发板/核心板

myd-sam9g35 工控板/开发板/核心板

myd-sam9x25 工控板/开发板/核心板

myd-sam9x35 工控板/开发板/核心板

mys-sam9g15 工控板/单板机

mys-sam9g25 工控板/单板机

mys-sam9g35 工控板/单板机

mys-sam9x25 工控板/单板机

mys-sam9x35 工控板/单板机

features

• vdd = 1.8 /- 0.1v
• vddq = 1.8 /- 0.1v
• all inputs and outputs are compatible with sstl_18 interface
• 8 banks
• fully differential clock inputs (ck, /ck) operation
• double data rate interface
• source synchronous-data transaction aligned to bidirectional data strobe (dqs, dqs)
• differential data strobe (dqs, dqs)
• data outputs on dqs, dqs edges when read (edged dq)
• data inputs on dqs centers when write (centered dq)
• on chip dll align dq, dqs and dqs transition with ck transition
• dm mask write data-in at the both rising and falling edges of the data strobe
• all addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• programmable cas latency 3, 4, 5 and 6 supported
• programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• programmable burst length 4/8 with both nibble sequential and interleave mode
• internal eight bank operations with single pulsed ras
• auto refresh and self refresh supported
• tras lockout supported
• 8k refresh cycles /64ms
• jedec standard 84ball fbga(x16)
• full strength driver option controlled by emr
• on die termination supported
• off chip driver impedance adjustment supported
• self-refresh high temperature entry
• average refresh cycle (tcase 0 oc~ 95 oc)
- 7.8 μs at 0oc ~ 85 oc
- 3.9 μs at 85oc ~ 95 oc
commercial temperature( 0oc ~ 85 oc)
industrial temperature( -40oc ~ 95 oc)